1. Field of the Invention
The disclosure relates in general to a method for manufacturing semiconductor device and structure manufactured by the same, more particularly to a method for manufacturing semiconductor device using self-aligned double-patterning process.
2. Description of the Related Art
A nonvolatile semiconductor memory device is typically designed to securely hold data even when power is lost or removed from the memory device. Various types of nonvolatile memory devices have been proposed in the related art. Also, manufactures have been looking for new developments or techniques combination for stacking multiple planes of memory cells, so as to achieve greater storage capacity. For example, several types of multi-layer stackable thin-film transistor (TFT) NAND-type flash memory structures have been proposed.
Recently, various 3D stacked structures, with single-gate unit cells, double gate unit cells and surrounding gate unit cells, have been provided. However, the more spaces occupied by the charge trapping multilayer (such as ONO multilayer), the more design rules to be considered in the size reduction of 3D stacked structure, which raises the difficulties of reducing size of unit cell. Compared to the 3D stacked structures with single-gate unit cells (each unit cell having one side ONO layer), the 3D stacked structures with double gate unit cells and surrounding gate unit cells would limit the potential and ability for size reduction. Moreover, if the thickness of the charge trapping multilayer is too thin, it would induce the issue of charge retention. Therefore, the thickness of the charge trapping multilayer has to be sufficient for charge retention when size of cell unit is reduced. To reduce the size of the 3D stacked structures, the charge trapping multilayer is not the only factor to be consider, considerations of design rules for other elements and effects on the electrical performance have to be included. The 3D stacked structures with double gate unit cells and surrounding gate unit cells are more complicated than that with single gate unit cells, which increase the difficulty of design and cost of manufacturing process.
Thus, it is desirable to develop a 3D memory structure not only with larger number of multiple planes being stacked to achieve greater storage capacity, but also with smaller unit cells and excellent electrical properties (such as reliability and stability of data storage), so that the smaller memory elements still can be erased and programmed. Moreover, the reduced dimensions of the 3D memory structures might create the thinner and higher patterns. The thin and high patterns (ex: an aspect ratio of a height of the pattern to its width is too high) of the 3D memory structure would be fallen down or bended easily during the manufacturing process. Therefore, it is one of the important goals to develop the related procedures for making the thinner but solid patterns of the 3D memory structure. Accordingly, it is desirable to fabricate a 3D memory structure with high speed and solid construction, and that 3D memory structure is also manufactured by not complicated manufacturing process thereby diminishing the manufacturing cost.